1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a lower substrate, an IPS mode liquid crystal display device and method for manufacturing the same.
2. Description of the Related Art
Generally, the liquid crystal display (LCD) device is manufactured by attaching an upper substrate to a lower substrate and injecting a liquid crystal between the upper and the lower substrates. A polarizing film and a retardation film have been attached to the outer surfaces of the upper and the lower substrates. An LCD device manufactured in this manner has a brightness and a high contrast because of changing the direction of light incident or changing a refractive index.
Normally, the LCD device incorporates a twisted nematic (TN) mode liquid crystal. However, such a TN-mode LCD device is not suitable for realizing a large-sized screen because the light transmittance changes in the gray scale display depending on a viewing angle.
To solve this problem, the in-plane switching (IPS) mode LCD device, which uses a horizontal electric field, has been suggested. The IPS mode LCD device has advantages in that contrast characteristics and viewing angle characteristics, for example, gray inversion and color shift are improved, as compared to the TN mode LCD device.
In the IPS mode LCD device, a pixel electrode and a common electrode are formed in the same plane on the lower substrate where a thin film transistor is arranged. At this time, the liquid crystal is operated by a fringe field formed between the pixel electrode and the common electrode. A color filter layer where a red sub-filter R, a green sub-filter G, and a blue sub-filter B having the sequential arrangement are formed on the upper substrate facing the lower substrate. The color filter layer can be formed by a pigment dispersing method, a dyeing, or a deposition method.
FIG. 1 is a partial plane view of a lower substrate of the IPS mode LCD device according to the related art. Referring to FIG. 1, on the lower substrate of the IPS mode LCD device according to the related art, a gate line 11 and a data line 13 are formed perpendicularly to cross each other, and a common electrode 15 is formed in parallel and in the same direction with the gate line 11.
A pixel region P is defined by the intersection of the gate line 11 and the data line 13. And, pixel region P includes the common electrode 15 and the pixel electrode 17 forming a finger shape, and patterned in an integrated manner. Namely, the common electrode 15 formed in parallel and in the same direction with the gate line 11, has a plurality of common electrode bars 15a formed vertically protruding and extending from the common electrode 15.
At the cross point where the gate line 11 and the data line 13 intersects each other, a thin film transistor T as a switching device is formed. The thin film transistor T includes a gate electrode 19 connected to the gate line 11, a source electrode 21 connected to the data line 13, and a drain electrode 23 connected to the pixel electrode 17. As in the case of the common electrode 15, a plurality of pixel electrode bars 17a are formed vertically to protrude and extend from the pixel electrode 17. The plurality of pixel electrode bars 17a and the plurality of common electrode bars 15a are alternately integrated.
Accordingly, when a predetermined voltage is applied to the pixel electrode 17 and the common electrode 15, a fringe field is distributed between each of the pixel electrode bars 17a and each of the common electrode bars 15a. The alignment of the liquid crystal molecules is varied depending on the fringe field, where an image is displayed.
However, in the IPS mode LCD device of the related art, as shown in FIG. 1, part A and part B (e.g., region between the data line 13 and the outermost pixel electrode bar 17a) represented by a dotted line at both ends of the pixel region P do not correspond to the pixel electrode bar 17a nor the common electrode bar 15a. Unlike the central region of the pixel region P, the liquid crystals disposed on the parts A and the B cannot operate properly, thus becoming a major factor in image quality deterioration.
To solve such a problem, a black matrix (hereinafter referred to as BM) layer is formed on a specific region on the upper substrate (not shown) that corresponds to the matching lower substrate. Namely, the BM layer is formed on the region of the upper substrates that corresponds to the rest region where the pixel electrode bars 17a and the common electrode bars 15a are formed. Since the BM layer is formed on the upper substrate that corresponds to the above-described A and B parts, it is possible to prevent light from being leaked out of parts A and B, except the display region. However, there still exists a problem that the aperture ratio is reduced as the region where the BM layer is formed is widened.
To overcome such a problem, a structure has been developed to cover a part of the upper part of the data line 13 by the common electrode bars 15a protruded and extended from the common electrode 15.
FIG. 2 is a partial plane view of a lower substrate in another IPS mode LCD device according to the related art. To solve the above problem, an insulating layer (not shown) made of a transparent organic insulating material (for example, photo acryl) having a low dielectric constant is disposed on a data line 113. A common electrode 115, a plurality of common electrode bars 115a, a pixel electrode 117, and a plurality of pixel electrode bars 117a are formed on the insulating layer. At this time, the common electrode bars 115a are partially formed over the data line 113.
As shown in FIG. 2, the lower substrate is provided with a gate line 111, the data line 113 is perpendicularly intersecting the gate line 111, and the common electrode 115 is formed in parallel with and in the same direction as the gate line 111. A pixel region (P) is defined by the intersection of the gate line 111 and the data line 113.
The common electrode 115 and the pixel electrode 117 are patterned in a finger-shaped structure integrating in the pixel region (P). The common electrode 115 has the plurality of common electrode bars 115a vertically protruding therefrom. And, the plurality of common electrode bars 115a are partly overlapping the data line 113.
At an intersection point of the gate line 111 and the data line 113, a thin film transistor (T) is formed as a switching element. The thin film transistor (T) has a gate electrode 119 connected to the gate line 111, a source electrode 121 connected to the data line 113 and a drain electrode 123 connected to the pixel electrode 117.
The pixel electrode 117 has the plurality of pixel electrode bars 117a vertically protruding from the pixel electrode 117, like in the common electrode 115. And, the pixel electrode bars 117a are integrated with the common electrode bars 115a. 
Accordingly, since the related art IPS mode liquid crystal display device shown in FIG. 2 has the common electrode bar formed even on the data line 113, as compared to FIG. 1, a fringe field is distributed in wider areas (i.e., regions A and B in FIG. 1). Accordingly, the IPS mode LCD device operates normally. Therefore, even though a black matrix (BM) layer is not formed on an upper substrate corresponding to the regions A and B shown in FIG. 1, the related art IPS mode LCD device shown in FIG. 2 can improve the aperture ratio.
FIGS. 3A to 3C are sectional views illustrating a manufacturing method taken along cross-sectional lines I—I and II—II of FIG. 2.
First, as shown in FIG. 3A, a conductive metal is deposited and patterned on a substrate 109 to form a gate line 111 and a gate electrode 119. Next, an inorganic insulating material (for example, a silicon nitride film (SiNx) and a silicon oxide film (SiO2)) or an organic insulating material (for example, acryl resin or benzocyclobutene (BCB)) is deposited on an entire surface of the substrate 109 including the gate line 111 thereby forming a gate insulating layer 118.
Thereafter, as shown in FIG. 3B, an intrinsic amorphous silicon (a-Si) and an impurity-doped amorphous silicon (n+ a-Si) are deposited on the entire gate insulating layer 118. Thereafter, the resultants are patterned to form an active layer 125 and an ohmic contact layer 127. Next, a conductive metal is deposited and patterned on the ohmic contact layer 127, thereby forming the data line 113, the source electrode 121 and the drain electrode 123.
After that, a low dielectric constant material (for example, BCB or acryl resin) is deposited on an entire surface of the substrate including the data line 113 and the like, thereby forming a passivation layer 129, and is patterned to form a drain contact hole 131 such that a portion of the drain electrode 123 is exposed to an exterior.
As shown in FIG. 3C, a transparent conductive metal (for example, indium-tin-oxide (ITO) and indium-zinc-oxide (IZO)) is deposited and patterned to form common electrode bars 115a and pixel electrode bars 117a, such that they are integrated with each other. Further, the common electrode 115 and the pixel electrode 117 are respectively formed to be connected with the common electrode bars 115a and the pixel electrode bars 117a. At this time, some of the common electrode bars 115a are overlapped with the data line 113 with interposing the passivation layer 129 therebetween.
By doing so, the related art IPS mode LCD device in FIG. 2 overcomes the drawback in which the liquid crystal molecules are abnormally operated in the regions A and B of FIG. 1 to deteriorate picture quality, thereby improving the aperture ratio. However, in the related art IPS mode LCD device of FIG. 2, the passivation layer 129 has a heavy thickness at a lower side of the common electrode 115 and the pixel electrode 117. Accordingly, the related art IPS mode LCD device in FIG. 2. has a disadvantage in that a back light (not shown), irradiated from the external of the substrate, has a reduced light transmittance due to the thick passivation layer 129.
FIG. 4 is a sectional view of the lower substrate taken along cross-sectional lines I—I and II—II of FIG. 2, and an upper substrate corresponding to the matching lower substrate.
Referring to FIG. 4, a further description regarding the lower substrate will be omitted since the lower substrate is identical with that of FIG. 3C. The upper substrate 140 facing the lower substrate includes a color filter layer 144 having a red (R) sub-color filter, a green (G) sub-color filter, and a blue (B) sub-color filter, in which an appropriate color filter layer is provided to match with each of the pixel regions (P) provided at the lower substrate. A BM layer 142 is formed to cover the region between the sub-color filters and a thin film transistor portion of the lower substrate. An over coat (hereinafter, referred to as “OC”) layer 146 is formed on the color filter layer 144 and the BM layer 142. At this time, a liquid crystal layer (not shown) is interposed between the upper substrate 140 and the lower substrate 109.
The aforementioned related art IPS mode LCD device has a drawback of a complex process and a high manufacturing cost due to the color filter layer 144, the BM film 142 and the OC layer 146 formed on the upper substrate 140. Further, it has a drawback in that the upper substrate did not have a construction referred as a cell combination margin of the upper and lower substrates, when the upper substrate was attached with the lower substrate.
Recently, there is proposed a structure in which a color filter layer is formed on a lower substrate to prevent the misalignment of the LCD device and a BM layer having a reduced width to improve an aperture ratio. A structure of forming the color filter layer under a thin film transistor (TFT) is called as a thin film transistor on color filter (TOC), and a structure of forming a color filter layer over the TFT is called as a color filter on thin film transistor (COT).
In the TOC structure, only the BM layer and the OC layer are formed on the upper substrate. At this time, the BM layer is able to not only preventing light from being leaked through regions other than a pixel region, but also shielding light from being incident to the TFT, thereby preventing optical current from being generated. However, when the BM layer is provided on the upper substrate, there is a drawback in that a slant incident light or some light reflected from the BM layer film cannot be prevent since the BM layer film and the TFT are spaced apart from each other.